The present invention relates generally to gain control circuits for providing variable gain in response to control signals. More particularly, it relates to gain control circuits that include current-steering transistors and provide specific, well-defined amounts of gain without requiring elaborate control-signal-generating circuitry.
Gain control circuits, typically implemented as automatic gain control circuits (AGCs), provide variable amplification or attenuation (i.e., gain) to an input signal. Automatic gain control circuits are often used in radio receivers to maintain a desired output signal level despite variation in the input signal level. One common type of gain control circuit employs a transconductance circuit to convert an input voltage to a current and then selectively controls current steering transistors to direct a desired amount of that current to an output load.
For example, a basic differential pair of current steering circuit may employ two matched bipolar junction transistors. The emitter terminals of the two transistors are connected together at a common node that is biased by the converted input current. The collector of the first transistor is coupled to VCC by way of an output load, while the collector of the second transistor is coupled to VCC directly. The base terminal of the first transistor receives a first gain control signal, and the base terminal of the second transistor receives a second control signal. In a maximum gain state, all of the converted current is directed through the first transistor that is coupled to the output. This requires that the first control signal be at least a certain threshold level larger than the second control signal so that the second transistor shuts off in this gain state. On the other hand, in a zero gain state, no current flows through the first transistor. In this state the second control signal must be larger than the first control signal by at least the threshold level so that the first transistor shuts off. When the control signals are equal, a middle gain state results in which half the current is directed through the first transistor. These three gain states are well-defined since they correspond to readily reproducible control signal conditions that occur when the control signals are equal or when the difference between the signals need not be exact but rather must only exceed a certain threshold. Such control signal conditions do not require elaborate and sophisticated circuitry since the control signals need not exactly differ by a specific non-zero amount to provide the corresponding gain.
At the same time, in many applications a non-zero minimum gain is required for proper operation of subsequent circuitry, such as a cascaded fixed gain amplifier circuit. In conventional current-steering gain control circuits, such as the one described above, this requires that a transistor steer a small but well-defined current to the output whenever the circuit is operating in the minimum gain state. The control signals must differ by a specific non-zero amount in order to direct the specific non-zero current to the output. However, without employing sophisticated control-signal-generating circuitry, it is difficult to provide the necessary control signals to do so. Similarly, between the minimum and maximum gain states of prior art current steering gain control circuits, it is difficult to achieve well-defined intermediate gain states that also correspond to easily reproducible control signal states.
Consequently, there is a need for a current steering-type gain control circuit that can consistently provide a non-zero minimum gain, without requiring additional complexity and cost in the control signal-generating circuitry. Such a circuit would provide additional advantages if it could also operate in a plurality of well-defined gain states that accurately and consistently provide gain values between the minimum and maximum gain levels. It would further be desirable if the well-defined minimum and intermediate gain value levels could be determined by the conductivity and physical properties of the current-steering transistors themselves, and without requiring additional circuit components or complexity.
The present invention provides a current steering-type gain control circuit capable of providing a non-zero minimum gain in response to readily reproducible control signal conditions that do not require sophisticated control-signal-generating circuitry. The gain control circuit is adapted from a conventional differential pair of current-steering transistors, biased by first and second control signals respectively, in which one of the transistors steers current that it conducts through an output and the other does not. To provide the well-defined non-zero minimum gain, the gain control circuit of the present invention includes at least one additional current steering transistor (in a single-ended implementation) that further steers current to the output when it conducts, as it does in the minimum gain state. The minimum gain value, can conveniently be selected by varying the physical characteristicsxe2x80x94e.g., saturation currents or conductivity parametersxe2x80x94of the current steering transistors, which may be bipolar or field effect transistors.
Preferably, in a single-ended configuration, a transconductance circuit is used to convert an input voltage into a proportional current which is then provided to the current steering transistors. A desired amount of the transconductance current is directed to a load impedance at the output so that it can be converted back into an output voltage. In a differential configuration, the input voltage is the difference between first and second input voltage signals which are respectively converted into first and second currents by a transconductance circuit. First and second symmetrical sets of current steering transistors are then used to direct a desired proportion of the first and second currents to first and second outputs respectively.
Thus, in one embodiment, the present invention provides a gain control circuit for steering a desired amount of a first current at common node through an output. The gain control circuit comprises a first, second, and third transistor. The first transistor is coupled between the common node and the output. The first transistor has a control terminal (e.g., a base terminal for a BJT or a gate terminal for a FET) for receiving a first control signal. The second transistor is coupled to the common node and has a control terminal for receiving a second control signal. The third transistor is coupled between the common node and the output. The third transistor has a control terminal which also preferably receives the second control signal. In this manner, current conducted by the first and third transistors is steered through the output, and current conducted by the second transistor is not steered through the output.
The transistors may be bipolar junction transistors (BJTs) such as heterojunction bipolar junction transistors (HBTs). In this case, the saturation current characteristics of the transistors are preferably not all equal, i.e., at least one transistor""s characteristic differs from the others. The ratio of the saturation current characteristics of the transistors is preferably determined by the ratio of the emitter-base junction areas of the transistors. In one embodiment, the first and third transistors have saturation current characteristics that are matched, and the second transistor has a saturation current characteristic that is different from the saturation current characteristic of the first and third transistors. Alternatively, the transistors may be field effect transistors, e.g., metal semiconductor field effect transistors (MESFETs). In this case, the transistors preferably have aspect ratios characteristics that are not all equal, where the aspect ratio of a transistor is defined as the channel width W divided by the channel length L.
In one embodiment, the gain control circuit further comprises at least one additional pair of current steering transistors. The first transistor in each additional pair is coupled to the common node and has a control terminal for receiving a further control signal specific to that transistor pair. The second transistor in each additional pair is coupled between the common node and the output and has a control terminal that also receives the control signal specific to that pair. Current conducted by the first transistor in each additional pair is not steered through the output, while current conducted by the second transistor in each additional pair is steered through the output. In this manner, the gain control circuit can provide a plurality of well-defined gain values between the maximum and minimum gain of the circuit. These well-defined intermediate gain values, may also be selected and varied by changing the physical characteristics of the current steering transistors. In this embodiment, the second transistor in each additional pair may have a current characteristic that is matched to the first and third transistors, while the first transistor in each additional pair preferably has a saturation current characteristic that is different from the saturation current characteristic of any other transistor.
In another embodiment, the present invention also provides a gain control circuit similar to that described above, but in a differential configuration. The differentially configured gain control circuit comprises a first set of transistors (as above) for steering a desired amount of a first current at a first common node through a first output. Similarly, the circuit further includes a second set of transistors for steering a desired amount of a second current at a second common node through a second output. The two sets of transistors are symmetric, so that the transistors in the first set match corresponding transistors in the second set. Corresponding transistors in each set also receive the same control signals. Again, the transistors may be BJTs or FETs.